US 12,225,707 B2
Method for manufacturing semiconductor structure, semiconductor structure and semiconductor memory
Xingsong Su, Hefei (CN); Weiping Bai, Hefei (CN); and Deyuan Xiao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 15, 2022, as Appl. No. 17/819,817.
Application 17/819,817 is a continuation of application No. PCT/CN2022/099844, filed on Jun. 20, 2022.
Claims priority of application No. 202210316932.1 (CN), filed on Mar. 28, 2022.
Prior Publication US 2023/0328955 A1, Oct. 12, 2023
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/038 (2023.02) [H10B 12/37 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
patterning the substrate to form a substrate layer and a plurality of silicon pillars;
forming an oxide layer on a surface of the substrate layer between the plurality of silicon pillars;
forming an isolation structure on the oxide layer, gaps being provided between upper part of the isolation structure and the silicon pillars;
forming a first conductive layer in the gaps;
partially removing the isolation structure and retaining the isolation structure below the first conductive layer to form an isolation layer; and
forming a dielectric layer and a second conductive layer on surfaces of the isolation layer, the oxide layer, the first conductive layer and the silicon pillars.