US 12,225,705 B2
Memory device having error detection function, semiconductor device, and electronic device
Hitoshi Kunitake, Isehara (JP); Tatsuya Onuki, Atsugi (JP); Tomoaki Atsumi, Hadano (JP); and Kiyoshi Kato, Atsugi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/419,745
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
PCT Filed Feb. 11, 2020, PCT No. PCT/IB2020/051043
§ 371(c)(1), (2) Date Jun. 30, 2021,
PCT Pub. No. WO2020/170069, PCT Pub. Date Aug. 27, 2020.
Claims priority of application No. 2019-030525 (JP), filed on Feb. 22, 2019.
Prior Publication US 2022/0085019 A1, Mar. 17, 2022
Int. Cl. H01L 29/78 (2006.01); G11C 29/52 (2006.01); H01L 29/786 (2006.01); H10B 12/00 (2023.01)
CPC H10B 12/00 (2023.02) [G11C 29/52 (2013.01); H01L 29/7869 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A memory device comprising:
a first element layer comprising a memory cell;
a second element layer comprising an error detection circuit;
a semiconductor substrate comprising a driver circuit; and
a sense amplifier and a precharge circuit,
wherein the second element layer is positioned between the semiconductor substrate and the first element layer,
wherein the memory cell comprises a first transistor,
wherein the error detection circuit comprises a second transistor,
wherein the driver circuit comprises a third transistor,
wherein the sense amplifier comprises a fourth transistor,
wherein the precharge circuit comprises a fifth transistor,
wherein the first transistor and the second transistor each comprise a metal oxide in a channel formation region,
wherein the third transistor comprises silicon in a channel formation region,
wherein the first transistor and the second transistor each comprise a front gate and a back gate,
wherein the second element layer further comprises a switch circuit,
wherein the switch circuit comprises a first switch,
wherein a bit line provided in a direction perpendicular to the semiconductor substrate is electrically connected to the fourth transistor and the fifth transistor via a sixth transistor, and
wherein an output signal of the error detection circuit is output to the driver circuit through the first switch of the switch circuit.