US 12,225,658 B2
Interlaced crosstalk controlled traces, vias, and capacitors
Shadi Ebrahimi Asl, Cary, NC (US); Stephen Aubrey Scearce, Apex, NC (US); Quinn Gaumer, Durham, NC (US); and Linda W. Scott, Winter Springs, FL (US)
Assigned to CISCO TECHNOLOGY, INC., San Jose, CA (US)
Filed by Cisco Technology, Inc., San Jose, CA (US)
Filed on Jul. 24, 2023, as Appl. No. 18/357,440.
Application 18/357,440 is a division of application No. 17/335,591, filed on Jun. 1, 2021, granted, now 11,785,706.
Prior Publication US 2023/0371169 A1, Nov. 16, 2023
Int. Cl. H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01); H05K 3/00 (2006.01); H05K 3/30 (2006.01); H05K 3/42 (2006.01)
CPC H05K 1/0218 (2013.01) [H05K 1/0298 (2013.01); H05K 1/115 (2013.01); H05K 1/181 (2013.01); H05K 3/0047 (2013.01); H05K 3/303 (2013.01); H05K 3/42 (2013.01); H05K 1/0219 (2013.01); H05K 1/0231 (2013.01); H05K 1/0245 (2013.01); H05K 2201/10015 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
routing, on a first internal layer of a multilayer printed circuit board, a first pair of traces, electrically connected to first vias of a first trace and via structure, between second vias of a second trace and via structure;
routing, on a second internal layer of the multilayer printed circuit board, a second pair of traces, electrically connected to the second vias of the second trace and via structure, between the first vias of the first trace and via structure;
backdrilling the first vias of the first trace and via structure to a first depth; and
backdrilling the second vias of the second trace and via structure to a second depth that is deeper than the first depth,
wherein the first vias of the first trace and via structure are separated by a first distance and the second vias of the second trace and via structure are separated by a second distance that is less than the first distance.