CPC H04W 72/53 (2023.01) [H04L 5/0092 (2013.01); H04L 5/0094 (2013.01); H04L 5/0098 (2013.01); H04W 8/24 (2013.01); H04W 72/046 (2013.01); H04W 72/23 (2023.01)] | 20 Claims |
1. An apparatus for wireless communication, comprising:
one or more memories storing processor-executable code; and
one or more processors coupled with the one or more memories, the one or more processors individually or collectively configured to execute the code to cause the apparatus to:
receive a downlink control information indicating a physical downlink shared channel multiplexing scheme and comprising one or more of an indication of a plurality of transmission configuration indicator states related to a physical downlink shared channel from a plurality of transmission reception points or an indication of one or more receive beams associated with the plurality of transmission configuration indicator states, wherein each of the plurality of transmission configuration indicator states is associated with a different transmission reception point of a plurality of transmission reception points;
decode the downlink control information; and
receive the physical downlink shared channel according to the physical downlink shared channel multiplexing scheme and from the plurality of transmission reception points and based at least in part on a difference between respective durations of a temporal period associated with the plurality of transmission configuration indicator states and a temporal offset period associated with the physical downlink shared channel from the plurality of transmission reception points,
wherein the physical downlink shared channel is received according to one or more of the plurality of transmission configuration indicator states, the one or more receive beams associated with the plurality of transmission configuration indicator states or one or more default receive beams.
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