| CPC H04W 72/046 (2013.01) [H04B 7/04 (2013.01); H04W 56/0015 (2013.01); H04W 72/542 (2023.01); H01Q 1/246 (2013.01); H01Q 21/205 (2013.01); H04B 7/2656 (2013.01); H04W 16/28 (2013.01); H04W 56/0095 (2013.01)] | 20 Claims |

|
1. An apparatus for wireless communication, in a system comprising:
one or more processors;
one or more memories in electronic communication with the one or more processors; and
instructions stored in the one or more memories and operable, when executed by the one or more processors, to cause the apparatus to:
monitor a synchronization channel associated with a beamformed synchronization block of a synchronization slot; and
receive a synchronization signal associated with a first frequency portion associated with a downlink reception beam of the synchronization block and at least one of data or control information associated with a second frequency portion associated with the downlink reception beam of the synchronization block during the synchronization slot.
|