US 12,225,485 B2
Synchronization signal block burst with multiple subsets
Iyab Issam Sakhnini, San Diego, CA (US); Tao Luo, San Diego, CA (US); Jing Sun, San Diego, CA (US); and Xiaoxia Zhang, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Apr. 27, 2022, as Appl. No. 17/660,956.
Claims priority of provisional application 63/184,008, filed on May 4, 2021.
Prior Publication US 2022/0361125 A1, Nov. 10, 2022
Int. Cl. H04W 56/00 (2009.01); H04L 5/00 (2006.01); H04W 74/0808 (2024.01)
CPC H04W 56/0015 (2013.01) [H04L 5/0048 (2013.01); H04W 74/0808 (2013.01)] 30 Claims
OG exemplary drawing
 
1. A user equipment (UE) for wireless communication, comprising:
one or more memories; and
one or more processors coupled to the one or more memories, wherein the one or more memories include instructions executable by the one or more processors to cause the UE to:
receive a synchronization signal block (SSB) configuration that indicates SSB location information associated with an SSB burst, the SSB location information indicating one or more SSB positions corresponding to at least one SSB position subset of a plurality of SSB position subsets, wherein a maximum number of SSB beams associated with the at least one SSB position subset is less than a maximum number of SSB beams associated with a transmission window; and
receive an SSB based at least in part on the SSB configuration.