CPC H04W 52/0229 (2013.01) [H04L 5/0051 (2013.01); H04W 52/0216 (2013.01); H04W 68/00 (2013.01); H04W 72/23 (2023.01)] | 14 Claims |
1. An apparatus, comprising:
one or more processors; and
one or more memories having instructions stored thereon that, when executed by the one or more processors, cause the apparatus to:
receive a first wake-up signal, wherein
the first wake-up signal is one of K wake-up signals,
K is an integer greater than or equal to 1, and
the K wake-up signals are quasi co-located with K synchronization signal blocks (SSBs), K channel state information-reference signals (CSI-RSs), or K demodulation reference signals (DMRSs);
determine M paging occasions and a first physical downlink control channel PDCCH) monitoring occasion in the M paging occasions, wherein
there is a correspondence between the K wake-up signals and the M paging occasions, there is a correspondence between the first wake-up signal and the first PDCCH monitoring occasion, and one of the M paging occasions comprises K PDCCH monitoring occasions, and the first PDCCH monitoring occasion is one of the K PDCCH monitoring occasions, and
M is an integer greater than or equal to 1;
receive downlink control information (DCI) used for paging on the first PDCCH monitoring occasion in the M paging occasions.
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