	US 12,225,314 B2
	Imaging device and electronic device
Seiichi Yoneda, Kanagawa (JP); Yusuke Negoro, Osaka (JP); Takeya Hirose, Kanagawa (JP); Shunsuke Sato, Kanagawa (JP); and Shunpei Yamazaki, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Appl. No. 17/995,803
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Apr. 9, 2021, PCT No. PCT/IB2021/052939 § 371(c)(1), (2) Date Oct. 7, 2022, PCT Pub. No. WO2021/209868, PCT Pub. Date Oct. 21, 2021.
Claims priority of application No. 2020-073767 (JP), filed on Apr. 17, 2020.
Prior Publication US 2023/0156376 A1, May 18, 2023
Int. Cl. H04N 25/78 (2023.01); H04N 25/771 (2023.01); H04N 25/79 (2023.01); H10K 39/32 (2023.01)

CPC H04N 25/78 (2023.01) [H04N 25/771 (2023.01); H04N 25/79 (2023.01); H10K 39/32 (2023.02)]

15 Claims

1. An imaging device comprising:

a plurality of pixel blocks each comprising a plurality of pixels and a memory cell; and

a first circuit configured to read out a maximum value of the analog data stored in the memory cell included in each of the plurality of pixel blocks,

wherein analog data calculated from data generated by the plurality of pixels is configured to be stored in the memory cell,

wherein the memory cell comprises a sixth transistor, a seventh transistor and a second capacitor, and

wherein one of a source and a drain of the sixth transistor, one electrode of the second capacitor, and a gate of the seventh transistor are electrically connected to each other.