US 12,225,313 B2
Image capturing device and image capturing apparatus
Sota Nakanishi, Kawasaki (JP); Shigeru Matsumoto, Sagamihara (JP); and Tomoki Hirata, Tokyo (JP)
Assigned to NIKON CORPORATION, Tokyo (JP)
Appl. No. 17/800,433
Filed by NIKON CORPORATION, Tokyo (JP)
PCT Filed Feb. 17, 2021, PCT No. PCT/JP2021/006011
§ 371(c)(1), (2) Date Aug. 17, 2022,
PCT Pub. No. WO2021/166979, PCT Pub. Date Aug. 26, 2021.
Claims priority of application No. 2020-024780 (JP), filed on Feb. 17, 2020; and application No. 2020-024781 (JP), filed on Feb. 17, 2020.
Prior Publication US 2023/0126104 A1, Apr. 27, 2023
Int. Cl. H04N 25/771 (2023.01); H01L 27/146 (2006.01); H04N 25/50 (2023.01); H04N 25/766 (2023.01)
CPC H04N 25/771 (2023.01) [H01L 27/14634 (2013.01); H04N 25/50 (2023.01); H04N 25/766 (2023.01)] 54 Claims
OG exemplary drawing
 
1. An image capturing device comprising:
a first semiconductor substrate including
a first pixel block including a first photoelectric converting unit configured to convert light into electric charges; and
a second pixel block containing a second photoelectric converting unit configured to convert light into electric charges; and
a second semiconductor substrate stacked with the first semiconductor substrate, the second semiconductor substrate including
a first control block including a first circuit unit, in which a first transistor for processing an analog signal is provided, and a second circuit unit, in which a second transistor for processing a digital signal is provided, and being configured to control an accumulation time of the electric charges converted by the first photoelectric converting unit; and
a second control block (i) arranged next to the first control block, (ii) including a third circuit unit, in which a third transistor for processing an analog signal is provided, and a fourth circuit unit, in which a fourth transistor for processing a digital signal is provided, and (iii) being configured to control an accumulation time of the electric charges converted by the second photoelectric converting unit,
wherein the first circuit unit and the third circuit unit are formed in a well region provided in the second semiconductor substrate.