US 12,225,220 B2
Encoder, decoder, and medium
Kiyofumi Abe, Osaka (JP); Takahiro Nishi, Nara (JP); Tadamasa Toma, Osaka (JP); and Yusuke Kato, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Mar. 2, 2022, as Appl. No. 17/684,657.
Application 17/684,657 is a continuation of application No. PCT/JP2020/036390, filed on Sep. 25, 2020.
Claims priority of provisional application 62/907,115, filed on Sep. 27, 2019.
Prior Publication US 2022/0191525 A1, Jun. 16, 2022
Int. Cl. H04N 19/423 (2014.01); H04N 19/159 (2014.01); H04N 19/176 (2014.01); H04N 19/82 (2014.01)
CPC H04N 19/423 (2014.11) [H04N 19/159 (2014.11); H04N 19/176 (2014.11); H04N 19/82 (2014.11)] 3 Claims
OG exemplary drawing
 
1. An encoder comprising:
circuitry; and
memory coupled to the circuitry,
wherein, in operation, the circuitry:
encodes a position and a shape of a region of each of a plurality of subpictures included in a picture, the plurality of subpictures being determined according to a constraint condition that: (i) one of a plurality of tiles included in a picture is not allowed to be partially included in one of the plurality of subpictures included in the picture; (ii) one of the plurality of subpictures is not allowed to be partially included in the one of the plurality of tiles; (iii) two or more of the plurality of subpictures are allowed to be included in the one of the plurality of tiles; and (iv) two or more of the plurality of tiles are allowed to be included in the one of the plurality of subpictures.