| CPC H04N 19/146 (2014.11) [H04N 19/105 (2014.11); H04N 19/159 (2014.11); H04N 19/176 (2014.11); H04N 19/184 (2014.11)] | 36 Claims | 

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               1. An apparatus comprising: 
            one or more processors; and 
                memory storing instructions that, when executed by the one or more processors, cause the device to: 
              receive, at a first bitrate, at least one segment of a first variant, wherein the at least one segment of the first variant comprises stream access points (SAPs) of a first type that do not reset a picture reference buffer; 
                  send a request for segments encoded at a second bitrate; and 
                  receive, at the second bitrate, a segment, of a second variant, that comprises a SAP of a second type that does reset the picture reference buffer, and a next segment of the second variant comprising a SAP of the first type. 
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