US 12,225,126 B2
Apparatus and method for detecting errors during data encryption
Wun-Jhe Wu, Kinmen County (TW); Po-Hung Chen, Taoyuan (TW); Chiao-Wen Cheng, Zhubei (TW); Jiun-Hung Yu, Zhubei (TW); and Chih-Wei Liu, Zhubei (TW)
Assigned to SILICON MOTION, INC., Zhubei (TW)
Filed by Silicon Motion, Inc., Zhubei (TW)
Filed on Dec. 7, 2022, as Appl. No. 18/076,615.
Claims priority of provisional application 63/292,038, filed on Dec. 21, 2021.
Claims priority of application No. 202211207303.1 (CN), filed on Sep. 30, 2022.
Prior Publication US 2023/0198754 A1, Jun. 22, 2023
Int. Cl. H04L 9/06 (2006.01); H04L 9/08 (2006.01)
CPC H04L 9/0891 (2013.01) [H04L 9/0631 (2013.01); H04L 9/0861 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus for detecting errors during data encryption, comprising:
a key generation circuitry, arranged operably to realize a key expansion operation for generating a plurality of round keys based on a root key in an encryption algorithm, wherein the encryption algorithm encodes plaintext or an intermediate encryption result with one round key in a corresponding round; and
a key-error detection circuitry, coupled to the key generation circuitry, arranged operably to: calculate redundant data corresponding to each round key; and output an error signal to a processing unit when finding that any round key does not match corresponding redundant data at a check point during the key expansion operation,
wherein each round key is divided into 16 subkeys, the subkeys are organized in an array of 4×4 bytes, each subkey is one byte, and the redundant data comprises an in-subkey parity bit corresponding to each subkey and an across-subkey parity 9-bit corresponding to each column of the array,
wherein the key-error detection circuitry is arranged operably to: output the error signal to the processing unit when finding that any subkey does not match a corresponding in-subkey parity bit, or the subkeys in any column with four corresponding in-subkey parity bits do not match a corresponding across-subkey parity 9-bit at the check point during the key expansion operation.