| CPC H04L 49/9052 (2013.01) [H04J 3/0632 (2013.01); G06F 2213/0026 (2013.01)] | 20 Claims |

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1. A system comprising:
a data buffer circuit that is configured to buffer data in a data buffer that comprises a plurality of columns; and
a lane shifter circuit coupled to the data buffer circuit and configured to perform operations comprising:
accessing a plurality of data elements comprising two data elements from each column of the plurality of columns; and
based on detecting a skip ordered set in the accessed plurality of data elements, the skip ordered set comprising fewer symbols than a number of columns in the plurality of columns, generating an output that comprises a number of output data elements equal to the number of columns, two of the output data elements having been accessed from a single column of the plurality of columns.
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