CPC H04L 1/0004 (2013.01) [H04L 1/0001 (2013.01); H04L 1/1614 (2013.01); H04L 1/1812 (2013.01); H04W 72/0446 (2013.01); H04W 72/0453 (2013.01); H04W 72/23 (2023.01); H04L 5/001 (2013.01)] | 7 Claims |
1. An integrated circuit for controlling an apparatus, the integrated circuit comprising:
transceiver circuitry, which, in operation, receives a signal comprising control information for scheduling a physical channel, wherein the control information includes:
a value indicative of a number of multiple subframes, wherein each subframe of the multiple subframes comprises a first transport block (TB) and a second TB,
a redundancy version (RV) indication, and
a first modulation and coding scheme (MCS) indicator for the first TB and a second MCS indicator for the second TB, which are common for the multiple subframes; and
processing circuitry, which is coupled to the transceiver circuitry and which, responsive to the first MCS indicator taking a value of a specific MCS indicator and the RV indication taking a defined value, the specific MCS indicator not used to indicate MCS when the RV indication takes the defined value, determines that all of the first TBs in the multiple subframes are disabled and, responsive to the second MCS indicator taking a value of the specific MCS indicator and the RV indication taking the defined value, determines that all of the second TBs in the multiple subframes are disabled.
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