US 12,224,773 B2
Circuitry for encoding a bus signal and associated methods
Clemens Gerhardus Johannes de Haas, Ewijk (NL); and Rigor Hendrikus Lambertus van der Heijden, Nijmegen (NL)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., San Jose, CA (US)
Filed on Nov. 14, 2022, as Appl. No. 18/055,288.
Claims priority of application No. 21212543 (EP), filed on Dec. 6, 2021.
Prior Publication US 2023/0179225 A1, Jun. 8, 2023
Int. Cl. H03M 7/12 (2006.01); H03M 5/12 (2006.01); H04L 12/40 (2006.01)
CPC H03M 5/12 (2013.01) [H04L 12/40 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
an input terminal for receiving an input signal indicative of signalling from a network, the input signal comprising at least a two level signal that comprises either a first voltage level or a second voltage level, an encoder configured to encode the input signal into an output signal and an output terminal for outputting the output signal, wherein the encoder is configured to:
detect a first edge in the input signal;
in response to the detection of the first edge provide a pulse generation sequence comprising the encoder being configured to:
generate, in the output signal, a first pulse, the first pulse comprising a first ramp portion in which the voltage level is changed from a first-pulse level to a second-pulse level, a first hold portion in which the second-pulse level is maintained, a second ramp portion in which the voltage level is changed from the second-pulse level to the first-pulse level and a second hold portion in which the first-pulse level is maintained, and wherein the first ramp portion and the first hold portion are provided at least over a first predetermined minimum time period and wherein the second ramp portion and the second hold portion are provided at least over a second predetermined minimum time period, and wherein the first pulse is provided over the first and second minimum time periods irrespective of an edge subsequent the first edge being present in the input signal; and
sample the input signal to obtain a first sample indicative of a voltage level of the input signal to which the input signal transitions following said detection of the first edge and store said first sample; and
sample the input signal a second time within a time window between the end of the first hold portion and an end of the first pulse to obtain a second sample indicative of a voltage level of the input signal and store said second sample; and
if the first sample and the second sample are indicative of different voltage levels, then the encoder is configured to generate, in the output signal, a second pulse, the second pulse comprising a first ramp portion in which the voltage level is changed from the first-pulse level to the second-pulse level, a first hold portion in which the second-pulse level is maintained, a second ramp portion in which the voltage level is changed from the second-pulse level to the first-pulse level and a second hold portion in which the first-pulse level is maintained, and wherein the first ramp portion and the first hold portion are provided at least over a third predetermined minimum time period and wherein the second ramp portion and the second hold portion are provided at least over a fourth predetermined minimum time period; or
if the first sample and the second sample are indicative of the same voltage levels, then the encoder is configured to maintain the voltage level in the output signal at the first-pulse level.