US 12,224,768 B2
Error correction method, error correction circuit and electronic device applying the same
Ho-Yin Chen, Hsinchu (TW); Han-Hsien Wang, Hsinchu (TW); and Han-Nung Yeh, Hsinchu (TW)
Assigned to ETRON TECHNOLOGY, INC., Hsinchu (TW)
Filed by ETRON TECHNOLOGY, INC., Hsinchu (TW)
Filed on Jul. 3, 2023, as Appl. No. 18/217,892.
Application 18/217,892 is a continuation of application No. 17/827,029, filed on May 27, 2022, granted, now 11,736,121.
Prior Publication US 2023/0387938 A1, Nov. 30, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03M 13/09 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/098 (2013.01) [H03M 13/1108 (2013.01); H03M 13/6597 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An error correction method of an electronic device including a decoder and an error code correction (ECC) engine, the error correction method comprising:
determining by the decoder whether an input analog code is at a forbidden state;
when the input analog code is at the forbidden state, setting by the decoder a digital binary code as a first predetermined code and inputting the digital binary code to the ECC engine from the decoder;
determining by the ECC engine whether the digital binary code from the decoder has a plurality of errors; and
when the digital binary code from the decoder has the plurality of errors, the ECC engine informing the decoder, resetting by the decoder the digital binary code as a second predetermined code and inputting the digital binary code from the decoder to the ECC engine for ECC.