CPC H03M 1/662 (2013.01) [H03M 1/0624 (2013.01); H03M 1/0854 (2013.01)] | 12 Claims |
1. A signal processing apparatus, comprising:
a plurality of time-interleaving digital-to-analog converters (sub-DACs), each configured to sample a digital input signal at a preset sub-DAC sample frequency, and to generate an analog sub-DAC output signal;
an analog multiplexer configured to sample the plurality of sub-DAC output signals at a preset multiplexer clock frequency, and to generate a multiplexer output signal;
a local analog-to-digital converter (ADC), configured to receive the multiplexer output signal and generate a digital feedback signal;
a digital compensation engine configured to receive the digital feedback signal from the local ADC and determine one or more distortion compensation parameters based on a comparison of the digital feedback signal with the digital input signal; and
a digital pre-processing stage configured to receive the one or more distortion compensation parameters from the digital compensation engine and perform distortion compensation pre-processing on the digital input signal.
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