US 12,224,765 B1
SAR ADC capable of full-scale voltage auto-tuning and method for the same
Boon-Eu Seow, Penang (MY); and Kei-Tee Tiew, Penang (MY)
Assigned to PIXART IMAGING INCORPORATION, Hsinchu (TW)
Filed by PixArt Imaging Incorporation, Hsinchu (TW)
Filed on Mar. 31, 2023, as Appl. No. 18/194,172.
Int. Cl. H03M 1/18 (2006.01); H03M 1/38 (2006.01); H03M 1/00 (2006.01); H03M 1/12 (2006.01)
CPC H03M 1/18 (2013.01) [H03M 1/38 (2013.01); H03M 1/00 (2013.01); H03M 1/12 (2013.01); H03M 1/124 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A successive approximation register analog-to-digital converter (SAR ADC), comprising:
at least one sub-ADC, wherein each of the at least one sub-ADC is configured to convert a corresponding input signal to a corresponding SAR code; and
a tuning control unit, configured to adjust a full-scale voltage of each of the sub-ADC to a corresponding predetermined target level in a VFS tuning mode;
wherein each of the at least one sub-ADC includes:
a sample-and-hold circuit, configured to operably generate a sample-and-hold signal by sample-and-holding the input signal;
a capacitive digital-to-analog converter (CDAC), configured to operably generate a DAC output signal according to the SAR code;
a comparator, configured to operably compare the sample-and-hold signal and the DAC output signal to generate a comparison signal;
a SAR logic circuit, configured to operably generate the SAR code according to the comparison signal using a binary successive approximation register conversion method; and
an adjusting capacitor array, coupled to an output terminal of the CDAC and configured to operably adjust an equivalent capacitance on the output terminal of the CDAC;
wherein in the VFS tuning mode, the tuning control unit is configured to operably generate a capacitor tuning code to adjust the equivalent capacitance on the output terminal of the CDAC, so as to adjust a full-scale voltage of each of the at least one sub-ADC to the predetermined target level according to the following steps:
S100: setting the capacitor tuning code to an initial code;
S201: adjusting the input signal to plural reference voltages;
S202: controlling the sub-ADC to convert the plural reference voltages to corresponding plural digital reference codes;
S203: extrapolating plural pairs of the plural reference voltages versus the plural digital reference codes to obtain a calibrating full-scale voltage corresponding to the capacitor tuning code;
S300: determining whether a difference between the calibrating full-scale voltage and the predetermined full-scale voltage level is meeting a target, wherein if the difference is meeting the target, entering a step S800, else entering a step S400;
S400: updating the capacitor tuning code according to the difference and return to the step S201; and
S800: memorizing the capacitor tuning code for the sub-ADC to operate with the full-scale voltage having the predetermined target level in a normal operation mode.