	US 12,224,763 B2
	Calibration method of capacitor array type successive approximation register analog-to-digital converter
Peng Xu, Hangzhou (CN)
Assigned to Shen An Micro Co., Ltd., Hangzhou (CN)
Filed by Shen An Micro Co., Ltd., Hangzhou (CN)
Filed on Dec. 5, 2022, as Appl. No. 18/075,213.
Claims priority of application No. 202111352391.X (CN), filed on Nov. 16, 2021.
Prior Publication US 2023/0198535 A1, Jun. 22, 2023
Int. Cl. H03M 1/10 (2006.01)

CPC H03M 1/1014 (2013.01)

9 Claims

1. A calibration method of a capacitor array type successive approximation register analog-to-digital converter comprising capacitors, wherein the capacitors of bits from low to high in the successive approximation register analog-to-digital converter are arranged with binary weight proportions, and the calibration method comprises:

obtaining an actual weight value of capacitors of a target bit and an error code between the actual weight value and an ideal weight value of the capacitors of the target bit;

calibrating an output code of the successive approximation register analog-to-digital converter to be calibrated with the error code by performing corresponding addition or subtraction to obtain a final calibrated output code,

wherein a capacitor array of the successive approximation register analog-to-digital converter comprises a positive capacitor array and a negative capacitor array, the step of obtaining the actual weight value of the capacitors of the target bit and the error code between the actual weight value and the ideal weight value of the capacitors of the target bit comprises:

initializing a positive capacitor of the target bit in the positive capacitor array and sampling;

switching plate voltage states of the capacitors of the target bit and capacitors of the lower bit next to the target bit through a logic control to obtain a first weight error voltage of the capacitors of the target bit;

converting the first weight error voltage using a differential analog-to-digital conversion to obtain a first weight error voltage code of the capacitors of the target bit, wherein the first weight error voltage code is represented by capacitors of bits from the bit next to the next lower bit of the target bit to the least significant bit;

initializing a negative capacitor of the target bit in the negative capacitor array and sampling;

switching plate voltage states of the capacitors of the target bit and capacitors of the lower bit next to the target bit through the logic control to obtain a second weight error voltage of the capacitors of the target bit;

converting the second weight error voltage using the differential analog-to-digital conversion to obtain a second weight error voltage code of the capacitors of the target bit, wherein the second weight error voltage code is represented by the capacitors of the bits from the bit next to the next lower bit of the target bit to the least significant bit;

obtaining the error code between the actual weight value and the ideal weight value of the capacitors of the target bit according to the first weight error voltage code and the second weight error voltage code,

wherein the capacitors of the target bit comprise the positive capacitor of the target bit and the negative capacitor of the target bit.