US 12,224,757 B2
Method and apparatus for reducing jitter in a phase-locked loop
Dustin Dale Forman, Kelowna (CA); Libin Timothy George, Kelowna (CA); Hassan Mohammadnavazi, Kelowna (CA); and Hu Jing Yao, Kelowna (CA)
Assigned to ESS Technology, Inc., Milpitas, CA (US)
Filed by ESS Technology, Inc., San Jose, CA (US)
Filed on Mar. 6, 2023, as Appl. No. 18/117,795.
Prior Publication US 2024/0305304 A1, Sep. 12, 2024
Int. Cl. H03L 7/091 (2006.01); H03L 7/089 (2006.01); H03L 7/099 (2006.01)
CPC H03L 7/091 (2013.01) [H03L 7/0891 (2013.01); H03L 7/099 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A phase-locked loop circuit comprising:
a digital voltage circuit configured to:
receive a loop feedback signal;
generate a divided feedback signal at a first voltage level from the loop feedback signal; and
generate an output frequency signal from the loop feedback signal;
a clock resampling circuit configured to:
receive the loop feedback signal and the divided feedback signal;
generate a resampled feedback signal at a second voltage level which is different from the first voltage level by resampling the divided feedback signal using the loop feedback signal;
an analog circuit feedback loop comprising:
a phase detector configured to:
receive a reference clock signal and the resampled feedback signal; and
generate a phase comparison signal by comparing a phase of the reference clock signal to a phase of the resampled feedback signal;
a low pass filter configured to receive and filter the phase comparison signal; and
a voltage controlled oscillator configured to:
receive the filtered phase comparison signal; and
generate the loop feedback signal from the filtered phase comparison signal; and
an output voltage circuit configured to generate a clock output signal from the output frequency signal.