US 12,224,756 B2
Clock and data recovery circuit using neural network circuit to obtain frequency difference information
Chien-Kai Kao, Hsinchu (TW); Shih-Che Hung, Hsinchu (TW); and Tse-Hsien Yeh, Hsinchu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MEDIATEK INC., Hsin-Chu (TW)
Filed on Jan. 30, 2023, as Appl. No. 18/103,472.
Claims priority of provisional application 63/367,632, filed on Jul. 4, 2022.
Prior Publication US 2024/0007110 A1, Jan. 4, 2024
Int. Cl. H04L 7/00 (2006.01); G06N 3/063 (2023.01); H03L 7/08 (2006.01); H03L 7/093 (2006.01)
CPC H03L 7/0807 (2013.01) [G06N 3/063 (2013.01); H03L 7/093 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A clock and data recovery (CDR) circuit, comprising:
a phase detector, configured to use a clock signal to sample an input signal to generate a plurality of phase detection results;
a neural network circuit, coupled to the phase detector, configured to receive the plurality of phase detection results to determine information of a frequency difference between the clock signal and the input signal;
a controller, configured to generate a control signal according to the information of the frequency difference between the clock signal and the input signal; and
a clock signal generator, configured to use the control signal to adjust a phase or frequency of the clock signal outputted to the phase detector.