US 12,224,754 B2
Frequency multiplier circuitry, corresponding system and vehicle
Giuseppe Papotto, Biancavilla (IT); Andrea Cavarra, Catania (IT); and Giuseppe Palmisano, S. Giovanni la Punta (IT)
Assigned to STMICROELECTRONICS S.R.L., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Jun. 10, 2022, as Appl. No. 17/838,159.
Claims priority of application No. 102021000016724 (IT), filed on Jun. 25, 2021.
Prior Publication US 2023/0018212 A1, Jan. 19, 2023
Int. Cl. H03K 5/00 (2006.01); G01S 13/931 (2020.01); H03F 3/20 (2006.01)
CPC H03K 5/00006 (2013.01) [G01S 13/931 (2013.01); H03F 3/20 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A circuit comprising:
frequency multiplier circuitry having input nodes configured to receive an input signal and an anti-phase version thereof, the input signal having a first frequency value, wherein the frequency multiplier circuitry is configured to produce a current signal at a second frequency value that is an even multiple of the first frequency value;
a transformer comprising a primary side and a secondary side, wherein the primary side comprises a primary inductance coupled to the frequency multiplier circuitry to receive the current signal therefrom, wherein the secondary side is configured to provide a frequency multiplied voltage signal, and wherein the frequency multiplier circuitry and the transformer are cascaded between at least one first node and a second node, the at least one first node and the second node couplable to a supply node and ground;
a first shunt resonator coupled between the supply node and the at least one first node;
a second shunt resonator coupled between the second node and the ground; and
a bypass current path coupled between the at least one first node and the second node.