US 12,224,752 B1
Clock gating circuit for dual-edge-triggered flip-flops
Yimai Peng, Cary, NC (US); Robert Joseph Vachon, Zebulon, NC (US); Daniel Yingling, Apex, NC (US); and Keith Alan Bowman, Morrisville, NC (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jul. 18, 2023, as Appl. No. 18/354,374.
Int. Cl. G06F 1/04 (2006.01); H03K 3/037 (2006.01); H03K 17/00 (2006.01); H03K 19/21 (2006.01)
CPC H03K 3/0372 (2013.01) [G06F 1/04 (2013.01); H03K 17/005 (2013.01); H03K 19/21 (2013.01)] 22 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a clock gating circuit (CGC), comprising:
a clock gating device configured to selectively gate or pass a selected clock signal based on an enable signal to generate an output clock signal; and
a clock selection circuit configured to select a non-complementary clock signal or a complementary clock signal to generate a select signal based on the output clock signal and the non-complementary clock signal or the complementary clock signal, and
an exclusive-NOR gate including a first input configured to receive the complementary clock signal, a second input configured to receive the select signal from the clock selection circuit, and an output configured to output the selected clock signal based on the select signal.