US 12,224,751 B2
Semiconductor device and semiconductor system having the same
Garoom Kim, Suwon-si (KR); and Jae-Woo Seo, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Dec. 20, 2022, as Appl. No. 18/085,185.
Claims priority of application No. 10-2022-0067983 (KR), filed on Jun. 3, 2022.
Prior Publication US 2023/0396241 A1, Dec. 7, 2023
Int. Cl. H03K 3/3562 (2006.01); H03K 3/012 (2006.01); H03K 3/037 (2006.01)
CPC H03K 3/0372 (2013.01) [H03K 3/012 (2013.01); H03K 3/35625 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
at least one flip-flop including a first flip-flop,
wherein the first flip-flop includes:
a first latch including a first data path receiving input data in response to a transmission signal and outputting middle data, and a first feedback path feeding the middle data back to the first data path; and
a second latch including a second data path receiving the middle data in response to the transmission signal and outputting output data, and a second feedback path feeding the output data back to the second data path, and
wherein at least one of the first feedback path and the second feedback path is disabled prior to enabling the first data path or the second data path,
wherein the flip-flop further includes:
a clock buffer configured to receive a reference clock signal, and generate an inverse clock signal and a delay clock signal from the reference clock signal as the transmission signal, and
wherein the second feedback path includes a second feedback inverter including a (2-1)-th PMOS feedback transistor and a (2-2)-th NMOS feedback transistor each gated by the output data, a (2-2)-th PMOS feedback transistor gated by the reference clock signal, and a (2-1)-th NMOS feedback transistor gated by the inverse clock signal.