US 12,224,747 B2
Semiconductor device related to calibrating termination resistance
Chae Sung Lim, Icheon-si (KR); Jung Taek You, Icheon-si (KR); Saeng Hwan Kim, Icheon-si (KR); Sang Sic Yoon, Icheon-si (KR); and Hong Joo Song, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jun. 28, 2023, as Appl. No. 18/343,537.
Application 18/343,537 is a continuation in part of application No. 18/116,001, filed on Mar. 1, 2023.
Claims priority of application No. 10-2022-0048459 (KR), filed on Apr. 19, 2022; application No. 10-2022-0055763 (KR), filed on May 4, 2022; and application No. 10-2022-0130003 (KR), filed on Oct. 11, 2022.
Prior Publication US 2023/0344429 A1, Oct. 26, 2023
Int. Cl. H03K 19/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01)
CPC H03K 19/0005 (2013.01) [G11C 7/10 (2013.01); G11C 7/222 (2013.01); G11C 2207/2254 (2013.01)] 26 Claims
OG exemplary drawing
 
1. A semiconductor system comprising:
a controller configured to transmit a command address, a first chip selection signal, and a second chip selection signal; and
a semiconductor device configured to receive the command address, the first chip selection signal, and the second chip selection signal, the semiconductor device including a first rank and a second rank that are configured to calibrate each termination resistance, based on the command address, the first chip selection signal, and the second chip selection signal,
wherein the first rank calibrates the termination resistance of the first rank to a target resistance, based on the command address and the first chip selection signal when a write operation on the first rank is performed, and
wherein the second rank calibrates the termination resistance of the second rank to a dynamic resistance, based on the command address and the second chip selection signal when a write operation on the second rank is performed.