| CPC H03K 17/6872 (2013.01) [H03L 7/08 (2013.01); H04B 1/40 (2013.01)] | 21 Claims |

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1. An apparatus, comprising:
a buffer configured to receive an input differential signal and generate an output signal based on the input differential signal, wherein the buffer comprises a first buffer stage comprising:
a first field effect transistor (FET);
a second FET coupled in series with the first FET between a first voltage rail and a second voltage rail;
a third FET;
a fourth FET coupled in series with the third FET between the first voltage rail and the second voltage rail, wherein the first and third FETs include gates coupled together, and wherein the second and fourth FETs include gates configured to receive positive and negative components of the input differential signal, respectively;
a first capacitor coupled between a drain of the second FET and the gates of the first and third FETs, and
a first resistor coupled between the drain of the second FET and the gates of the first and third FETs such that the first resistor is coupled in parallel with the first capacitor.
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