| CPC H03H 11/18 (2013.01) [H03H 11/20 (2013.01)] | 11 Claims |
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1. A phase shift circuit, comprising:
a signal generator configured to generate an in-phase signal, a complementary in-phase signal, a quadrature phase signal, and a complementary quadrature phase signal based on an input signal;
a controller configured to generate a first selection signal, a second selection signal, a first control signal, and a second control signal;
a vector adder; and
a digital-to-analog converter configured to generate a first bias signal, a second bias signal, a third bias signal, and a fourth bias signal based on the first control signal and the second control signal,
wherein the vector adder includes:
an input circuit;
a switching circuit configured to shift each of phases of a first internal signal, a second internal signal, a third internal signal, and a fourth internal signal received from the input circuit and output a first shift signal, a second shift signal, a third shift signal, and a fourth shift signal; and
an output circuit configured to generate an output signal based on the first to fourth shift signals,
wherein the input circuit includes:
a first transistor connected between a ground node for receiving ground power and a first node for generating the first internal signal and configured to operate based on the in-phase signal and the first bias signal;
a second transistor connected between the ground node and a second node for generating the second internal signal and configured to operate based on the complementary in-phase signal and the first bias signal;
a third transistor connected between the ground node and the first node and configured to operate based on the second bias signal;
a fourth transistor connected between the ground node and the second node and configured to operate based on the second bias signal;
a fifth transistor connected between the ground node and a third node for generating the third internal signal and configured to operate based on the quadrature phase signal and the second bias signal;
a sixth transistor connected between the ground node and a fourth node for generating the fourth internal signal and configured to operate based on the complementary quadrature phase signal and the second bias signal;
a seventh transistor connected between the ground node and the third node and configured to operate based on the first bias signal; and
an eighth transistor connected between the ground node and the fourth node and configured to operate based on the first bias signal, and wherein each of the first control signal and the second control signal includes N bits, where N is a natural number of 2 or more.
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