US 12,224,715 B2
Reference generation circuit for maintaining temperature-tracked linearity in amplifier with adjustable high-frequency gain
Suhas Rattan, London (GB)
Filed by Kandou Labs SA, Lausanne (CH)
Filed on Sep. 27, 2022, as Appl. No. 17/935,599.
Application 17/935,599 is a continuation of application No. 17/246,292, filed on Apr. 30, 2021, granted, now 11,456,708.
Prior Publication US 2023/0021200 A1, Jan. 19, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 1/30 (2006.01); H03F 3/16 (2006.01); H03G 3/30 (2006.01); H03G 5/16 (2006.01)
CPC H03F 1/301 (2013.01) [H03F 3/16 (2013.01); H03G 3/30 (2013.01); H03G 5/165 (2013.01); H03F 2200/447 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a receiver equalizer peaking circuit comprising a set of input field effect transistors (FETs), a capacitor Field Effect Transistor (CFET) having a capacitive value determined by a CFET control voltage and a resistor FET (RFET) having a resistive value determined by a RFET control voltage, the receiver equalizer peaking circuit configured to equalize an input signal received at the set of input FETs;
a capacitor controller digital-to-analog converter (DAC) operating according to a first reference voltage that varies proportionally to fluctuations in the threshold voltage of the input FETs, the capacitor controller DAC configured to map a capacitive digital code to the CFET control voltage which tracks the variations in the first reference voltage;
a resistor controller DAC operating according to a second reference voltage that varies proportionally to fluctuations in (i) the threshold voltage of the input FET and (ii) a threshold voltage of the RFET to maintain the resistive value, the resistor controller configured to generate the RFET control voltage, the resistor controller DAC configured to map a resistive digital code to the RFET control voltage which tracks the variations in the second reference voltage; and
a reference generation circuit configured to generate the first and second reference voltages, the reference generation circuit comprising a replica input FET to track the fluctuations in the threshold voltage of the input FETs and a replica RFET to track the fluctuations in the threshold voltage of the RFET.