US 12,224,713 B2
Multiple-stage Doherty power amplifiers implemented with multiple semiconductor technologies
Mark Pieter van der Heijden, Eindhoven (NL); Joseph Staudinger, Gilbert, AZ (US); and Elie A. Maalouf, Mesa, AZ (US)
Assigned to NXP USA, Inc., Austin, TX (US)
Filed by NXP USA, Inc., Austin, TX (US)
Filed on Jun. 28, 2021, as Appl. No. 17/360,821.
Prior Publication US 2022/0416725 A1, Dec. 29, 2022
Int. Cl. H03F 1/02 (2006.01); H01L 23/66 (2006.01); H03F 3/195 (2006.01); H03F 3/21 (2006.01); H03F 3/213 (2006.01)
CPC H03F 1/0288 (2013.01) [H01L 23/66 (2013.01); H03F 3/211 (2013.01); H01L 2223/6644 (2013.01); H03F 2200/451 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An amplifier, comprising:
a substrate with a mounting surface;
a first power transistor die coupled to the mounting surface, wherein the first power transistor die includes a first III-V semiconductor substrate, a first radio frequency (RF) signal input terminal, a first RF signal output terminal, and a first transistor, wherein the first transistor has a first control terminal electrically coupled to the first RF signal input terminal, and a first current-carrying terminal electrically coupled to the first RF signal output terminal;
a second power transistor die coupled to the mounting surface, wherein the second power transistor die includes a second III-V semiconductor substrate, a second radio frequency (RF) signal input terminal, a second RF signal output terminal, and a second transistor, wherein the second transistor has a second control terminal electrically coupled to the first RF signal input terminal, and a second current-carrying terminal electrically coupled to the first RF signal output terminal;
a third die coupled to the mounting surface, the third die includes at least one of silicon germanium (SiGe), gallium arsenide (GaAs), and indium phosphide (InP), a third RF signal input terminal, a third RF signal output terminal that is electrically connected to the first RF signal input terminal, a first amplification path between the third RF signal input terminal and the third RF signal output terminal, a fourth RF signal input terminal, a fourth RF signal output terminal that is electrically connected to the second RF signal input terminal, and a second amplification path between the fourth RF signal input terminal and the fourth RF signal output terminal, wherein the first amplification path includes a first heterojunction bipolar transistor (HBT) coupled between the third RF signal input terminal and the third RF signal output terminal and the second amplification path includes a second HBT coupled between the fourth RF signal input terminal and the fourth RF signal output terminal, wherein a first bias control circuit is coupled to a first base of the first HBT and a second bias control circuit is coupled to a second base of the second HBT, and wherein the third die includes a first variable capacitance, a first terminal of the first variable capacitance is electrically connected to a collector of the second HBT, and a second terminal of the first variable capacitance is electrically connected to the base of the first HBT; and
a first connection electrically coupled between the second RF signal output terminal and the first RF signal output terminal.