US 12,224,657 B2
Power converting device
Takayoshi Miki, Tokyo (JP); and Kohei Onda, Tokyo (JP)
Assigned to Mitsubishi Electric Corporation, Tokyo (JP)
Appl. No. 17/996,536
Filed by Mitsubishi Electric Corporation, Tokyo (JP)
PCT Filed Jun. 17, 2020, PCT No. PCT/JP2020/023727
§ 371(c)(1), (2) Date Oct. 19, 2022,
PCT Pub. No. WO2021/255850, PCT Pub. Date Dec. 23, 2021.
Prior Publication US 2023/0223834 A1, Jul. 13, 2023
Int. Cl. H02M 7/5395 (2006.01); H02M 1/088 (2006.01); H03K 17/687 (2006.01)
CPC H02M 1/088 (2013.01) [H02M 7/5395 (2013.01); H03K 17/6871 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A power converter comprising:
an upper-arm semiconductor switching element and a lower-arm semiconductor switching element connected in series between a positive-side input terminal and a negative-side input terminal;
an upper-arm gate drive circuit configured to drive the upper-arm semiconductor switching element and including an upper-arm time point detection circuit configured to detect a time point at which a voltage between main terminals of the upper-arm semiconductor switching element has crossed a first reference voltage;
a lower-arm gate drive circuit configured to drive the lower-arm semiconductor switching element and including a lower-arm time point detection circuit configured to detect a time point at which a voltage between main terminals of the lower-arm semiconductor switching element has crossed a second reference voltage; and
a controller including
a calculator configured to calculate a change time point of an output voltage outputted from a connection portion between the upper-arm semiconductor switching element and the lower-arm semiconductor switching element, and
a PWM command pulse generator configured to generate, on the basis of information about the time point calculated by the calculator, a PWM command pulse to be given to the upper-arm gate drive circuit and the lower-arm gate drive circuit, wherein
each of the upper-arm time point detection circuit and the lower-arm time point detection circuit includes
a voltage division circuit configured to divide or reduce the voltage between the main terminals of the respective semiconductor switching element,
a comparator configured to compare an output from the voltage division circuit with the corresponding one of the first reference voltage and the second reference voltage, and detect and output a time point at which the voltage between the main terminals of the semiconductor switching element has been changed, and
a filter disposed between the voltage division circuit and the comparator and having a time constant smaller than a change time period of the voltage between the main terminals of the semiconductor switching element.