US 12,224,482 B2
Antenna effect protection and electrostatic discharge protection for three-dimensional integrated circuit
Po-Hsiang Huang, Tainan (TW); Fong-Yuan Chang, Hsinchu County (TW); Tsui-Ping Wang, Zhubei (TW); and Yi-Shin Chu, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Aug. 10, 2023, as Appl. No. 18/448,045.
Application 18/448,045 is a continuation of application No. 17/815,411, filed on Jul. 27, 2022, granted, now 11,824,254.
Application 17/815,411 is a continuation of application No. 17/149,853, filed on Jan. 15, 2021, granted, now 11,437,708, issued on Sep. 6, 2022.
Claims priority of provisional application 63/002,737, filed on Mar. 31, 2020.
Prior Publication US 2024/0120639 A1, Apr. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01Q 1/22 (2006.01); H01L 23/66 (2006.01); H01Q 1/50 (2006.01); H01Q 23/00 (2006.01)
CPC H01Q 1/2283 (2013.01) [H01L 23/66 (2013.01); H01Q 1/50 (2013.01); H01Q 23/00 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A three-dimensional (3D) integrated circuit (IC) package, comprising:
a first IC die comprising a first substrate at a back side of the first IC die;
a second IC die stacked at the back side of the first IC die and facing the first substrate;
a through-substrate via (TSV) through the first substrate and electrically connecting the first IC die and the second IC die, the TSV comprising a TSV cell having a TSV cell boundary surrounding the TSV; and
at least one diode fabricated in the first substrate, wherein the at least one diode is electrically connected to the TSV, wherein the at least one diode is fabricated within the TSV cell boundary surrounding the TSV, and wherein no functional cell is fabricated within the TSV cell boundary.