US 12,224,376 B2
Light-emitting display device and electronic device including a first pixel and a second pixel and an oxide semiconductor region overlapping a light-emitting region
Ryo Arasawa, Kanagawa (JP); and Hideaki Shishido, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Jan. 19, 2024, as Appl. No. 18/417,474.
Application 15/131,119 is a division of application No. 13/936,355, filed on Jul. 8, 2013, granted, now 9,318,654, issued on Apr. 19, 2016.
Application 18/417,474 is a continuation of application No. 17/751,758, filed on May 24, 2022, granted, now 11,901,485.
Application 17/751,758 is a continuation of application No. 16/736,008, filed on Jan. 7, 2020, granted, now 11,355,669, issued on Jun. 7, 2022.
Application 16/736,008 is a continuation of application No. 16/531,204, filed on Aug. 5, 2019, granted, now 10,566,497, issued on Feb. 18, 2020.
Application 16/531,204 is a continuation of application No. 15/131,119, filed on Apr. 18, 2016, granted, now 10,411,158, issued on Sep. 10, 2019.
Application 13/936,355 is a continuation of application No. 12/897,299, filed on Oct. 4, 2010, granted, now 8,482,004, issued on Jul. 9, 2013.
Claims priority of application No. 2009-235180 (JP), filed on Oct. 9, 2009.
Prior Publication US 2024/0154060 A1, May 9, 2024
Int. Cl. H01L 33/16 (2010.01); H01L 27/12 (2006.01)
CPC H01L 33/16 (2013.01) [H01L 27/1225 (2013.01); H01L 27/124 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A display device comprising:
a first pixel including a first transistor, a second transistor, and a light-emitting element,
wherein one of a source and a drain of the first transistor is electrically connected to a gate electrode of the second transistor,
wherein the light-emitting element is electrically connected to one of a source and a drain of the second transistor,
wherein the other of the source and the drain of the second transistor is electrically connected to a power supply line,
wherein the first transistor includes a first channel formation region, and the second transistor includes a second channel formation region,
wherein the first channel formation region includes a first oxide semiconductor layer, and the second channel formation region includes a second oxide semiconductor layer,
wherein a first conductive layer configured to be a gate electrode of the first transistor and to be a first wiring overlaps the first oxide semiconductor layer,
wherein a second conductive layer configured to be the gate electrode of the second transistor overlaps the second oxide semiconductor layer,
wherein the power supply line includes a third conductive layer configured to be a second wiring,
wherein, in a plan view, a channel length direction of the first transistor is aligned with a channel length direction of the second transistor,
wherein, in the plan view, the first oxide semiconductor layer and the second oxide semiconductor layer do not have a region overlapping a light-emitting region of the first pixel, and
wherein, in the plan view, the first oxide semiconductor layer has a region overlapping a light-emitting region of a second pixel next to the first pixel.