US 12,224,358 B2
JBS device with improved electrical performances, and manufacturing process of the JBS device
Simone Rascuna′, Catania (IT); Gabriele Bellocchi, Catania (IT); and Marco Santoro, Messina (IT)
Assigned to STMicroelectronics S.R.L., Agrate Brianza (IT)
Filed by STMicroelectronics S.r.l., Agrate Brianza (IT)
Filed on Jan. 25, 2022, as Appl. No. 17/584,185.
Claims priority of application No. 102021000002333 (IT), filed on Feb. 3, 2021.
Prior Publication US 2022/0246770 A1, Aug. 4, 2022
Int. Cl. H01L 29/872 (2006.01); H01L 21/04 (2006.01); H01L 29/16 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/872 (2013.01) [H01L 21/046 (2013.01); H01L 29/1608 (2013.01); H01L 29/6606 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A Junction Barrier Schottky (JBS) device, comprising:
a semiconductor body of silicon carbide having a first type of electrical conductivity;
a first implanted region having a second type of electrical conductivity opposite to the first type of electrical conductivity and extending into the semiconductor body from a top surface of the semiconductor body, the first implanted region forming a first junction barrier (JB) diode with the semiconductor body;
a first electrical terminal in contact with the first implanted region and in direct electrical contact with the top surface of the semiconductor body, laterally to the first implanted region, the first electrical terminal forming a Schottky diode with the semiconductor body; and
an ohmic contact within the first implanted region and in contact with the first electrical terminal,
wherein the first implanted region physically and electrically separates the ohmic contact from the semiconductor body,
wherein an electrical resistivity value of the ohmic contact is lower than an electrical resistivity value of the first impalnted region,
wherein the first implanted region includes a first portion and a second portion electrically connected directly to each other and aligned with each other along a first alignment axis transverse to the top surface of the semiconductor body, the first portion of the first implanted region extending, along the first alignment axis, between the second portion of the first implanted region and the first electrical terminal,
wherein the first portion of the first implanted region has, orthogonally to the first alignment axis, a maximum width having a first value, and
wherein the second portion of the first implanted region has, orthogonally to the first alignment axis, a respective maximum width having a second value greater than the first value.