| CPC H01L 29/78696 (2013.01) [H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] | 20 Claims |
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1. A semiconductor device comprising:
a substrate;
active regions disposed on the substrate, the active regions including:
a first active region extending on the substrate in a horizontal direction parallel to an upper surface of the substrate, and
a second active region spaced apart from the first active region;
a plurality of channel layers disposed on the active regions, the plurality of channel layers including:
a plurality of first channel layers disposed on the first active region, wherein first channel layers of the plurality of first channel layers are spaced apart from each other in a vertical direction perpendicular to the upper surface of the substrate, and
a second channel layer disposed on the second active region;
gate structures disposed on the substrate, the gate structures including:
a first gate structure intersecting the first active region and the first channel layers, and
a second gate structure intersecting the second active region and the second channel layer; and
source/drain regions disposed on the active regions, the source/drain regions including:
a first source/drain region disposed on the first active region on at least one side of the first gate structure and contacting the plurality of first channel layers, and
a second source/drain region disposed on the second active region on at least one side of the second gate structure and contacting the second channel layer,
wherein the plurality of first channel layers includes a first uppermost channel layer and first lower channel layers disposed below the first uppermost channel layer, and the first uppermost channel layer includes a material that is different from a material included in the first lower channel layers.
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