US 12,224,356 B2
Thin film transistor and manufacturing method of same, and display device
Hiroyuki Ohta, Sakai (JP)
Assigned to SAKAI DISPLAY PRODUCTS CORPORATION, Sakai (JP)
Appl. No. 17/614,914
Filed by SAKAI DISPLAY PRODUCTS CORPORATION, Sakai (JP)
PCT Filed Jun. 4, 2019, PCT No. PCT/JP2019/022220
§ 371(c)(1), (2) Date Nov. 29, 2021,
PCT Pub. No. WO2020/245925, PCT Pub. Date Dec. 10, 2020.
Prior Publication US 2022/0238724 A1, Jul. 28, 2022
Int. Cl. H01L 29/786 (2006.01); H01L 29/12 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/78696 (2013.01) [H01L 29/127 (2013.01); H01L 29/66969 (2013.01); H01L 29/1054 (2013.01); H01L 29/78 (2013.01); H01L 29/7869 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A thin film transistor comprising:
a substrate;
an active layer supported on the substrate, the active layer including a first region, a second region, and a channel region located between the first region and the second region;
a gate electrode arranged so as to overlap at least the channel region of the active layer with a gate insulating layer therebetween;
a source electrode electrically connected to the first region of the active layer; and
a drain electrode electrically connected to the second region of the active layer, wherein
at least the channel region having a layered structure includes:
a lower oxide semiconductor layer;
a first metal layer that is continuous, and that is arranged on the lower oxide semiconductor layer and containing substantially no oxygen; and
an upper oxide semiconductor layer arranged on a top surface of the first metal layer, and
a thickness of the first metal layer is smaller than a thickness of the lower oxide semiconductor layer or a thickness of the upper oxide semiconductor layer.