US 12,224,349 B2
Self-aligned gate endcap (SAGE) architectures with vertical sidewalls
Ritesh K. Das, Hillsboro, OR (US); Kiran Chikkadi, Hillsboro, OR (US); and Ryan Pearce, Beaverton, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 7, 2020, as Appl. No. 16/868,828.
Prior Publication US 2021/0351300 A1, Nov. 11, 2021
Int. Cl. H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01)
CPC H01L 29/7855 (2013.01) [H01L 29/4983 (2013.01); H01L 29/7848 (2013.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a semiconductor fin having first and second sidewalls along a length of the semiconductor fin, the first and second sidewalls tapering outwardly from a distal end of the semiconductor fin to a substrate from which the semiconductor fin extends;
a trench isolation structure laterally adjacent to a portion of the semiconductor fin that is proximate the substrate;
a first gate endcap isolation structure having a length parallel with the length of the semiconductor fin, the first gate endcap isolation structure extending into the trench isolation structure, the first gate endcap isolation structure having a sidewall laterally facing the first sidewall of the semiconductor fin with the trench isolation structure therebetween, the first gate endcap isolation structure having a first width, wherein the sidewall of the first gate endcap isolation structure is substantially vertical;
a second gate endcap isolation structure having a length parallel with the length of the semiconductor fin, the second gate endcap isolation structure extending into the trench isolation structure, the second gate endcap isolation structure having a sidewall laterally facing the second sidewall of the semiconductor fin with the trench isolation structure therebetween, the second gate endcap isolation structure having a second width greater than the first width; and
a gate electrode in contact with the first and second gate endcap isolation structures, the second gate endcap isolation structure positioned at a lateral side of the gate electrode.