US 12,224,348 B2
Semiconductor device structure and method for forming the same
Kuo-Cheng Chiang, Zhubei (TW); Shi-Ning Ju, Hsinchu (TW); Ching-Wei Tsai, Hsinchu (TW); Kuan-Lun Cheng, Hsin-chu (TW); and Chih-Hao Wang, Baoshan Township, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 15, 2024, as Appl. No. 18/635,530.
Application 17/316,325 is a division of application No. 16/395,731, filed on Apr. 26, 2019, granted, now 11,038,058, issued on Jun. 15, 2021.
Application 18/635,530 is a continuation of application No. 18/304,422, filed on Apr. 21, 2023, granted, now 11,961,913.
Application 18/304,422 is a continuation of application No. 17/316,325, filed on May 10, 2021, granted, now 11,664,454, issued on May 30, 2023.
Prior Publication US 2024/0274717 A1, Aug. 15, 2024
Int. Cl. H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/785 (2013.01) [H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 27/0924 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device structure, comprising:
a plurality of nanowire structures over a channel region of a semiconductor fin structure;
a source/drain feature on a source/drain region of the semiconductor fin structure; and
a dielectric fin structure spaced apart from the source/drain feature and the semiconductor fin structure, wherein a top surface of the dielectric fin structure is higher than a top surface of a bottommost one of the nanowire structures, and a bottom surface of the dielectric fin structure is lower than a bottom surface of the source/drain feature.