US 12,224,347 B2
P-type field effect transistor (PFET) on a silicon germanium (Ge) buffer layer to increase Ge in the PFET source and drain to increase compression of the PFET channel and method of fabrication
Bin Yang, San Diego, CA (US); Xia Li, San Diego, CA (US); and Haining Yang, San Diego, CA (US)
Assigned to QUALCOMM INCORPORATED, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Feb. 19, 2021, as Appl. No. 17/180,219.
Prior Publication US 2022/0271162 A1, Aug. 25, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/161 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7848 (2013.01) [H01L 21/823814 (2013.01); H01L 27/092 (2013.01); H01L 29/161 (2013.01); H01L 29/66477 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a silicon substrate;
a buffer layer disposed on the silicon substrate, the buffer layer comprising a first percentage of germanium;
a silicon layer comprising a semiconductor material disposed on the buffer layer;
a first transistor comprising:
a first channel region of the silicon layer comprising the semiconductor material doped with a pentavalent impurity;
a first gate disposed on the first channel region;
a first source disposed on a first side of the first channel region on the buffer layer; and
a first drain disposed on a second side of the first channel region on the buffer layer;
wherein:
the first source and the first drain each comprise a silicon germanium (SiGe) composite comprising a second percentage of germanium, and the second percentage is greater than the first percentage; and
a second transistor comprising:
a second channel region of the silicon layer comprising the semiconductor material doped with a trivalent impurity;
a second gate disposed on the second channel region;
a second source disposed on a first side of the second gate and recessed into the silicon layer on the first side of the second gate; and
a second drain disposed on a second side of the second gate opposite the first side and recessed into the silicon layer on the second side of the second gate,
wherein:
a first portion of the silicon layer is disposed between the second source and the buffer layer; and
a second portion of the silicon layer is disposed between the second drain and the buffer layer.