US 12,224,346 B2
Domain switching devices and methods of manufacturing the same
Jinseong Heo, Suwon-si (KR); Sangwook Kim, Seongnam-si (KR); Yunseong Lee, Osan-si (KR); and Sanghyun Jo, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 13, 2023, as Appl. No. 18/486,493.
Application 18/486,493 is a continuation of application No. 18/060,372, filed on Nov. 30, 2022, granted, now 11,824,119.
Application 18/060,372 is a continuation of application No. 17/026,665, filed on Sep. 21, 2020, granted, now 11,527,646, issued on Dec. 13, 2022.
Claims priority of application No. 10-2019-0117483 (KR), filed on Sep. 24, 2019.
Prior Publication US 2024/0038890 A1, Feb. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/06 (2006.01); G11C 11/22 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/78391 (2014.09) [G11C 11/223 (2013.01); H01L 29/40111 (2019.08); H01L 29/6684 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a channel region;
a source and a drain connected to the channel region;
a gate electrode isolated from contact with the channel region;
an anti-ferroelectric layer between the channel region and the gate electrode;
a conductive layer between the gate electrode and the anti-ferroelectric layer, the conductive layer in contact with the anti-ferroelectric layer; and
a barrier layer between the anti-ferroelectric layer and the channel region,
wherein the anti-ferroelectric layer comprises zirconium oxide at a ratio of over 50% in adjacent region to the conductive layer and the anti-ferroelectric layer has non-hysteresis behavior characteristics.