US 12,224,345 B2
Semiconductor device
Kentaro Ichinoseki, Nonoichi Ishikawa (JP); Tatsuya Nishiwaki, Nonoichi Ishikawa (JP); and Shingo Sato, Kanazawa Ishikawa (JP)
Assigned to Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed by Kabushiki Kaisha Toshiba, Tokyo (JP); and Toshiba Electronic Devices & Storage Corporation, Tokyo (JP)
Filed on Oct. 18, 2023, as Appl. No. 18/489,389.
Application 18/489,389 is a continuation of application No. 17/699,898, filed on Mar. 21, 2022, granted, now 11,830,945.
Application 17/699,898 is a continuation of application No. 16/816,764, filed on Mar. 12, 2020, granted, now 11,322,612, issued on May 3, 2022.
Claims priority of application No. 2019-168488 (JP), filed on Sep. 17, 2019.
Prior Publication US 2024/0072167 A1, Feb. 29, 2024
Int. Cl. H01L 29/78 (2006.01); H01L 21/225 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7827 (2013.01) [H01L 21/2253 (2013.01); H01L 29/0634 (2013.01); H01L 29/0878 (2013.01); H01L 29/407 (2013.01); H01L 29/42368 (2013.01); H01L 29/4238 (2013.01); H01L 29/66666 (2013.01); H01L 29/7813 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first electrode;
a first semiconductor region provided on the first electrode and electrically connected to the first electrode, the first semiconductor region being of a first conductivity type;
a second electrode opposing a portion of the first semiconductor region in a second direction and a third direction with an insulating layer interposed, the second direction being perpendicular to a first direction from the first electrode toward the first semiconductor region, the third direction being perpendicular to the first direction and crossing the second direction, the second electrode having a circular configuration when viewed from the first direction;
a gate electrode provided in a grid pattern and enclosing a portion of the second electrodes along a first plane parallel to the second direction and the third direction;
a second semiconductor region opposing the gate electrode with a gate insulating layer interposed, being provided between the gate electrode and the second electrode, and being of a second conductivity type;
a third semiconductor region provided on the second semiconductor region, the third semiconductor region being of the first conductivity type; and
a third electrode provided on the second semiconductor region and the third semiconductor region and electrically connected to the second semiconductor region, the third semiconductor region, and the second electrode,
wherein
the third electrode includes a contact portion,
a lower surface of the contact portion directly contacts with the second electrode, and
a length in the third direction of the contact portion is longer than a length in the third direction of the second electrode.