US 12,224,344 B2
Method and system for control of sidewall orientation in vertical gallium nitride field effect transistors
Clifford Drowley, Santa Clara, CA (US); Andrew P. Edwards, Santa Clara, CA (US); Hao Cui, Santa Clara, CA (US); Subhash Srinivas Pidaparthi, Santa Clara, CA (US); Michael Craven, Santa Clara, CA (US); and David DeMuynck, Santa Clara, CA (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Mar. 29, 2022, as Appl. No. 17/707,835.
Claims priority of provisional application 63/172,525, filed on Apr. 8, 2021.
Prior Publication US 2022/0328688 A1, Oct. 13, 2022
Int. Cl. H01L 29/78 (2006.01); H01L 29/20 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7827 (2013.01) [H01L 29/2003 (2013.01); H01L 29/42384 (2013.01); H01L 29/66446 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A method of fabricating a field effect transistor (FET) on a III-nitride substrate, the method comprising:
providing the III-nitride substrate;
aligning a mask with respect to the III-nitride substrate;
forming a mask layer including a plurality of mask patterns;
providing a plurality of gate interface regions aligned parallel to one of the <1210> directions of the III-nitride substrate ±0.3° and adjoining a channel region extending between a source region and a drain region;
forming a plurality of gate regions in contact with the plurality of gate interface regions;
forming a gate electrode coupled to the plurality of gate regions;
forming a source electrode coupled to the source region; and
forming a drain electrode coupled to the drain region.