US 12,224,337 B2
PGaN enhancement mode HEMTs with dopant diffusion spacer
Michael Beumer, Portland, OR (US); Robert Ehlert, Portland, OR (US); Nicholas Minutillo, Beaverton, OR (US); Michael Robinson, Beaverton, OR (US); Patrick Wallace, Portland, OR (US); and Peter Wells, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/132,951.
Prior Publication US 2022/0199816 A1, Jun. 23, 2022
Int. Cl. H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/7786 (2013.01) [H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A Group III-nitride (III-N) transistor, comprising:
a channel layer comprising a first III-N material;
a polarization layer over the channel layer, wherein the polarization layer is a second III-N material with more Al than the first III-N material;
a p-type layer over the polarization layer, wherein the p-type layer is a third III-N material comprising a greater concentration of a P-type impurity than either the channel layer or the polarization layer;
a spacer layer between, and in contact with, the polarization layer and the p-type layer, wherein the spacer layer is the third III-N material, but with a lower concentration of the P-type impurity than the p-type layer;
a gate terminal over the spacer layer; and
source and drain terminals coupled to the channel layer.