| CPC H01L 29/66795 (2013.01) [H01L 29/7827 (2013.01); H01L 21/823418 (2013.01); H01L 21/845 (2013.01)] | 16 Claims |
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1. A semiconductor device, comprising:
semiconductor patterns each protruding from a substrate in a vertical direction perpendicular to an upper surface of the substrate;
conductive patterns surrounding upper sidewalls of the semiconductor patterns, respectively, the conductive patterns not covering upper surfaces of the semiconductor patterns;
a first insulating interlayer between the conductive patterns;
a lower impurity region at an upper portion of the substrate under a respective one of the semiconductor patterns, the lower impurity region contacting a lower surface of the respective one of semiconductor patterns;
an upper impurity region contacting an upper surface of the respective one of the semiconductor patterns;
a second insulating interlayer entirely covering an upper surface of the upper impurity region;
pads connected to the conductive patterns, respectively, the pads including substantially same conductive material as the conductive patterns; and
contact plugs on the pads, respectively,
wherein no electrical signals are applied to the lower and upper impurity regions, and electrical signals are applied to the conductive patterns through the contact plugs so that the conductive patterns and the first insulating interlayer are a capacitor.
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