US 12,224,334 B2
Semiconductor device with gate dielectric formed using selective deposition
Tung-Ying Lee, Hsinchu (TW); Tse-An Chen, Taoyuan (TW); Tzu-Chung Wang, Hsinchu (TW); Miin-Jang Chen, Taipei (TW); Yu-Tung Yin, Taipei (TW); and Meng-Chien Yang, Taoyuan (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); NATIONAL TAIWAN UNIVERSITY, Hsinchu (TW); and NATIONAL TAIWAN NORMAL UNIVERSITY, Taipei (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW); NATIONAL TAIWAN UNIVERSITY, Taipei (TW); and NATIONAL TAIWAN NORMAL UNIVERSITY, Taipei (TW)
Filed on May 26, 2023, as Appl. No. 18/324,636.
Application 18/324,636 is a continuation of application No. 17/586,083, filed on Jan. 27, 2022, granted, now 11,699,739.
Application 17/586,083 is a continuation of application No. 16/844,809, filed on Apr. 9, 2020, granted, now 11,245,024, issued on Feb. 8, 2022.
Prior Publication US 2023/0317820 A1, Oct. 5, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/28 (2006.01); H01L 21/02 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/6653 (2013.01) [H01L 21/02603 (2013.01); H01L 21/28141 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66545 (2013.01); H01L 29/66742 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of semiconductor layers arranged one above another;
source/drain epitaxial regions on opposite sides of the plurality of semiconductor layers;
a gate structure surrounding each of the plurality of semiconductor layers, the gate structure comprising interfacial layers respectively over the plurality of semiconductor layers, a high-k dielectric layer over the interfacial layers, and a gate metal over the high-k dielectric layer; and
gate spacers spacing apart the gate structure from the source/drain epitaxial regions, wherein a top position of the high-k dielectric layer is lower than top positions of the gate spacers, and the high-k dielectric layer is spaced apart from one of the gate spacers by a void region.