US 12,224,330 B2
Silicide structures in transistors and methods of forming
Kai-Di Tzeng, Hsinchu (TW); Chen-Ming Lee, Yangmei (TW); Fu-Kai Yang, Hsinchu (TW); and Mei-Yun Wang, Chu-Pei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 27, 2023, as Appl. No. 18/520,326.
Application 17/826,673 is a division of application No. 16/881,384, filed on May 22, 2020, granted, now 11,349,005, issued on May 31, 2022.
Application 18/520,326 is a continuation of application No. 17/826,673, filed on May 27, 2022, granted, now 11,855,169.
Prior Publication US 2024/0096999 A1, Mar. 21, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/45 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 29/40 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/45 (2013.01) [H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/401 (2013.01); H01L 29/41791 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
patterning an opening through an interlayer dielectric (ILD), wherein the opening exposes a surface of a source/drain region;
forming a silicide in the opening, wherein forming the silicide comprises:
performing a first deposition process to form a first metal-comprising portion on the source/drain region;
performing a second deposition process to form a second metal-comprising portion on the first metal-comprising portion; and
performing a passivation treatment on the second metal-comprising portion to convert the second metal-comprising portion to a nitride; and
forming a source/drain contact in the opening over the silicide.