US 12,224,326 B2
Contact architecture for capacitance reduction and satisfactory contact resistance
Rishabh Mehandru, Portland, OR (US); Pratik A. Patel, Portland, OR (US); Ralph T. Troeger, Portland, OR (US); and Szuya S. Liao, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Oct. 10, 2023, as Appl. No. 18/378,472.
Application 18/378,472 is a continuation of application No. 17/667,493, filed on Feb. 8, 2022, granted, now 11,824,097.
Application 17/667,493 is a continuation of application No. 17/085,857, filed on Oct. 30, 2020, granted, now 11,282,930, issued on Mar. 22, 2022.
Application 17/085,857 is a continuation of application No. 16/465,489, granted, now 10,872,960, issued on Dec. 22, 2020, previously published as PCT/US2016/069513, filed on Dec. 30, 2016.
Prior Publication US 2024/0038857 A1, Feb. 1, 2024
Int. Cl. H01L 29/417 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/321 (2006.01); H01L 29/08 (2006.01); H01L 29/40 (2006.01); H01L 29/45 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/4175 (2013.01) [H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/0262 (2013.01); H01L 21/26513 (2013.01); H01L 21/30604 (2013.01); H01L 21/32115 (2013.01); H01L 29/0847 (2013.01); H01L 29/401 (2013.01); H01L 29/45 (2013.01); H01L 29/4991 (2013.01); H01L 29/665 (2013.01); H01L 29/6656 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a fin comprising silicon;
a first epitaxial source or drain region and a second epitaxial source or drain region in the fin;
a first contact member on the first epitaxial source or drain region, and a second contact member on the second epitaxial source or drain region;
a first conductive interconnect on the first contact member, the first conductive interconnect having an uppermost surface;
a first dielectric layer adjacent to the first conductive interconnect, the first dielectric layer having an uppermost surface at a same level as the uppermost surface of the first conductive interconnect, the first dielectric layer in contact with the first epitaxial source or drain region, and the first dielectric layer having a first composition;
a second dielectric layer having a vertical interface with the first dielectric layer, the second dielectric layer having an uppermost surface at a same level as the uppermost surface of the first dielectric layer, and the second dielectric layer having a second composition different than the first composition;
a gate contact over the fin, the gate contact having a first side and a second side opposite the first side, wherein the second dielectric layer is between the first side of the gate contact and the first dielectric layer, the gate contact having an uppermost surface at a same level as the uppermost surface of the second dielectric layer;
a third dielectric layer adjacent to the second side of the gate contact, the third dielectric layer having an uppermost surface at a same level as the uppermost surface of the gate contact, and the third dielectric layer having the second composition;
a fourth dielectric layer having a vertical interface with the third dielectric layer, the fourth dielectric layer having an uppermost surface at a same level as the uppermost surface of the third dielectric layer, and the fourth dielectric layer having the first composition; and
a second conductive interconnect on the second contact member, the second conductive interconnect adjacent to the fourth dielectric layer, and the second conductive interconnect having an uppermost surface at a same level as the uppermost surface of the fourth dielectric layer.