US 12,224,324 B2
Method of forming backside power rails
Po-Yu Huang, Hsinchu (TW); Chen-Ming Lee, Taoyuan County (TW); I-Wen Wu, Hsinchu (TW); Fu-Kai Yang, Hsinchu (TW); and Mei-Yun Wang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Jul. 19, 2023, as Appl. No. 18/354,887.
Application 18/354,887 is a continuation of application No. 17/159,999, filed on Jan. 27, 2021, granted, now 11,728,394.
Prior Publication US 2023/0369418 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/40 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01)
CPC H01L 29/401 (2013.01) [H01L 21/7624 (2013.01); H01L 29/41775 (2013.01); H01L 29/66742 (2013.01); H01L 21/26506 (2013.01); H01L 21/26513 (2013.01); H01L 21/26586 (2013.01); H01L 21/30604 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 29/42392 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
receiving a workpiece including a fin structure over a front side of a substrate;
recessing a source region of the fin structure to form a source opening;
extending the source opening into the substrate to form a plug opening;
forming a semiconductor plug in the plug opening;
planarizing the substrate to expose the semiconductor plug from a back side of the substrate;
performing a first wet etching process to remove a portion of the substrate;
performing a pre-amorphous implantation (PAI) process to amorphize a rest portion of the substrate;
performing a second wet etching process to remove the amorphized rest portion of the substrate to form a dielectric opening;
depositing a dielectric layer in the dielectric opening; and
replacing the semiconductor plug with a backside source contact.