US 12,224,318 B2
Radio frequency transistor amplifiers having self-aligned double implanted source/drain regions for improved on-resistance performance and related methods
Kyle Bothe, Cary, NC (US); Chloe Hawes, Asheville, NC (US); Jennifer Gao, Burlington, NC (US); and Scott Sheppard, Chapel Hill, NC (US)
Assigned to Wolfspeed, Inc., Durham, NC (US)
Filed by Wolfspeed, Inc., Durham, NC (US)
Filed on Feb. 11, 2022, as Appl. No. 17/669,479.
Prior Publication US 2023/0261054 A1, Aug. 17, 2023
Int. Cl. H01L 29/08 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 29/66 (2006.01); H01L 29/778 (2006.01)
CPC H01L 29/0891 (2013.01) [H01L 21/26513 (2013.01); H01L 21/266 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01)] 27 Claims
OG exemplary drawing
 
16. A method of forming a high electron mobility transistor, the method comprising:
forming a semiconductor layer structure that comprises a Group III nitride-based channel layer and a Group III nitride-based barrier layer that has a higher bandgap than the Group III nitride-based channel layer on an upper surface of the Group III nitride-based channel layer;
forming a first source/drain region in the semiconductor layer structure, the first source/drain region including a first implanted region and a first auxiliary implanted region that merges with the first implanted region;
forming a second source/drain region in the semiconductor layer structure;
forming a gate finger on the semiconductor layer structure, the gate finger having a first longitudinal axis that extends parallel to an upper surface of the semiconductor layer structure;
forming a first source/drain contact on and above the first implanted region, the first source/drain contact having an inner sidewall that faces the gate finger and an outer sidewall opposite the inner sidewall;
forming a second source/drain contact on and above the second source/drain region, the second source/drain contact having an inner sidewall that faces the gate finger and an outer sidewall opposite the inner sidewall;
wherein a depth of the first implanted region is at least twice a depth of the first auxiliary implanted a region,
wherein the first source/drain region extends inwardly a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure and perpendicular to the longitudinal axis, and extends outwardly a second distance along the transverse axis from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region, where the first distance exceeds the second distance, and
wherein the first source/drain contact, the second source/drain contact and the gate finger are contacts of a first unit cell transistor.