US 12,224,314 B2
Size-controllable multi-stack semiconductor device and method of manufacturing the same
Gunho Jo, Albany, NY (US); Ki-il Kim, Albany, NY (US); Byounghak Hong, Albany, NY (US); and Kang-ill Seo, Albany, NY (US)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Aug. 13, 2021, as Appl. No. 17/402,214.
Claims priority of provisional application 63/174,655, filed on Apr. 14, 2021.
Prior Publication US 2022/0336582 A1, Oct. 20, 2022
Int. Cl. H01L 29/06 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01)
CPC H01L 29/0665 (2013.01) [H01L 27/0886 (2013.01); H01L 29/42392 (2013.01); H01L 29/66742 (2013.01); H01L 29/7851 (2013.01); H01L 29/78696 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A multi-stack semiconductor device comprising:
a substrate; and
a plurality of multi-stack transistor structures arranged on the substrate in a channel width direction,
wherein the multi-stack transistor structures comprise at least one lower transistor structure and at least one upper transistor structure stacked above the lower transistor structure,
wherein the lower and upper transistor structures comprise at least one channel layer as a current channel, and
wherein the lower transistor structures of at least two multi-stack transistor structures have different channel-layer widths such that a width of a channel layer of a lower transistor structure is different from a width of a channel layer of another lower transistor structure, among the lower transistor structures.