US 12,224,312 B2
Field effect transistors with bottom dielectric isolation
Julien Frougier, Albany, NY (US); Ruilong Xie, Niskayuna, NY (US); Andrew M. Greene, Slingerlands, NY (US); and Veeraraghavan S. Basker, Schenectady, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by International Business Machines Corporation, Armonk, NY (US)
Filed on Aug. 25, 2021, as Appl. No. 17/411,597.
Prior Publication US 2023/0060619 A1, Mar. 2, 2023
Int. Cl. H01L 27/088 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/0649 (2013.01) [H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01); H01L 29/0673 (2013.01); H01L 29/42392 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A field effect transistor (FET) device comprising:
an active region, the active region comprising a plurality of field effect transistors, a first edge and a second edge disposed opposite the first edge;
a dielectric isolation region disposed horizontally-beneath the active region and above an underlying semiconductor substrate, the dielectric isolation region further disposed vertically in gate diffusion break regions at the first edge and the second edge of the active region.